1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that is capable of eliminating a stain generated at an outer area of a thin film transistor array using an in-plane switching mode. The present invention also is directed to a liquid crystal display device that is capable of minimizing a time delay of a common voltage applied to a thin film transistor array area.
2. Discussion of the Related Art
Generally, a liquid crystal display of active matrix driving system uses thin film transistors (TFTs) as switching devices to display a natural moving picture. Since such a liquid crystal display can be made into a device that is smaller than a cathode ray tube (CRT), it is commercially available for use in monitors such as portable televisions, notebook personal computers and laptop personal computers, etc.
The active matrix liquid crystal display (LCD) displays a picture corresponding to video signals, such as television signals, on a pixel (or picture element) matrix having pixels arranged at each crossing of gate lines and data lines. Each pixel includes a liquid crystal cell for controlling transmitted light quantity in accordance with a voltage level of a data signal from a data line. The TFT is installed at the crossing of the gate line and the data line to switch a data signal to be transferred to the liquid crystal cell in response to a scanning signal (i.e., a gate pulse) from the gate line.
Such a liquid crystal display (LCD) can be largely classified as a twisted nematic (TN) mode, in which a vertical electric field is applied, or as an in-plane switching (IPS) mode, in which a horizontal electric field is applied to have a wide viewing angle. Which classification applies to the LCD depends on the direction of an electric field driving a liquid crystal.
The IPS mode LCD has an advantage over the TN mode LCD in that a liquid crystal within a pixel area is rotated in the horizontal direction by a horizontal electric field to have a wide viewing angle.
Referring to FIG. 1, the IPS mode LCD includes a TFT 50 provided at an intersection between a data line 52 and a gate line 54, pixel electrodes 48 arranged in a matrix in a pixel area between the data line 52 and the gate line 54, and a common electrode 35 formed in parallel to the pixel electrodes 48 in the pixel area. As shown in FIG. 2, the TFT 50 is provided on a rear substrate 32. The TFT 50 includes a gate electrode 34 connected to the gate line 54, a source electrode 42 connected to the data line 52, a drain electrode 44 connected to the pixel electrode 48, and an active layer 38 defining a channel between the source electrode 42 and the drain electrode 44.
The gate electrode 34, the gate line 54 and the common electrode 35 are formed by depositing a metal such as chrome (Cr), etc. on the rear substrate 32 and then patterning it. Herein, the common electrode 35 is patterned into a plurality of strips within the cell area. A gate insulating film 36 made from an inorganic dielectric material such as SiNx, etc. is entirely deposited on the rear substrate 32 provided with the gate electrode 34, the gate line 54 and the common electrode 35. Semiconductor layers consisting of the active layer 38 made from amorphous silicon (a-Si) and an ohmic contact layer 40 made from a-Si doped with n+ ions are disposed sequentially on the gate insulating film 36. Then, the source electrode 42, the drain electrode 44 and the data line 52 made from a metal material are provided to cover the semiconductor layers 38 and 40. In this case, the source electrode 42 and the drain electrode 44 are patterned in such a manner to be spaced by a predetermined channel width from each other. Thereafter, indium-tin-oxide (ITO) is deposited and then patterned to form the pixel electrode 48. Herein, the pixel electrode 48 is connected to the drain electrode 44 and is patterned into a plurality of strips that partially overlap and alternate with the common electrode 35 within the pixel area. Subsequently, an ohmic contact layer 40 is etched along a channel defined between the source electrode 42 and the drain electrode 44 to expose the active layer 38. A protective film 46 made from SiNx or SiOx, etc. is entirely deposited on the rear substrate 32 to cover and thus protect the TFT 50 and the pixel electrode 48.
As shown in FIG. 3, the rear substrate 32, which is provided with the TFT array, is opposed to a front substrate 72, which is provided with black matrices 74 and color filters 76. A liquid crystal layer 78 is interposed between the rear and front substrates. When a gate high pulse is applied to the gate electrode 34 of the TFT 50, an electric field corresponding to a difference voltage between a data voltage and a common voltage is applied between the pixel electrode 48 and the common electrode 35 during a scanning period when a channel is defined between the source electrode 42 and the drain electrode 44. Liquid crystal molecules of the liquid crystal layer 78 are driven with the horizontal electric field to control a quantity of transmitted light inputted from a back light.
Referring to FIG. 4, common voltage lines 87 for commonly applying a common voltage from an external driver to the common electrode 35 (FIG. 2) within a TFT array 90 are formed on the rear substrate 32 in parallel to the gate lines 54. The common voltage lines 87 within the TFT array 90 are formed at the outer area adjacent to the TFT array 90 and are connected, via common voltage pads 80, to the external driver. The gate line 54 is connected, via the gate pad 84 and a gate link 86, to the external driver. The gate link 86 formed at the outer area of the TFT array 90 connects the gate line 54 to the gate pad 84 to deliver a gate voltage from the external driver to the TFT array 90. Further, a plurality of data pads 82 and a plurality of data lines 52 for delivering a data voltage to the TFT array 90 are provided on the rear substrate 32. A liquid crystal 78 is injected between the rear substrate 32 and the front substrate 72 over the TFT array area, the gate pad area and the gate link area.
In this case, during the majority of a driving period, liquid crystal 93 at the gate link area is coupled with a direct current voltage caused by a gate voltage applied to the gate link 86 and a common voltage applied to the common voltage line 87 to thereby generate deterioration of liquid crystal.
More specifically, an electric field corresponding to a voltage difference between a data voltage of the pixel electrode 48 and a common voltage of the common electrode 35 (wherein the pixel electrode 48 is horizontally opposed to the common electrode 35 for each cell) is applied to the liquid crystal 78 of the TFT array 90 during a period when a gate high voltage is applied to the gate electrode 34 and is maintained during a period when a gate low voltage is applied. By this horizontal electric field, the liquid crystal 78 is driven for each cell to control a transmitted quantity of a light inputted from the back light. Generally, an electric field having the opposite polarity is applied to the liquid crystal 78 of the TFT array 90 for each frame so as to prevent deterioration of the liquid crystal. On the other hand, a voltage difference between a common voltage 5V and a gate voltage (i.e., a gate high voltage of +20V or a gate low voltage of −5V) is applied to the liquid crystal injected into an area at which the gate link 86 crosses the common voltage line 87 in the outer area of the TFT array 90. More specifically, a gate high voltage of about +20V is applied to each gate line 54 for a relatively short time during one frame period. A gate low voltage of about −5V is supplied in the remaining portion of the frame period, which is the majority of the frame period. Thus, a direct current voltage, which is a voltage difference between the common voltage and the gate low voltage, is applied to the liquid crystal at an area where the gate link 86 crosses the common voltage line 87 during most period to thereby cause deterioration of liquid crystal with the lapse of time. Moreover, the deteriorated liquid crystal in the gate link area is diffused into the liquid crystal in the vicinity of the edge of the TFT array 90. This is because the common voltage line 87 crossing the gate link 86 is adjacent to the TFT array 90. As a result, a stain is generated at the periphery of the LCD because of such liquid crystal deterioration thus degrading picture quality and reliability.
Furthermore, in the conventional LCD device, a large number of common voltage lines 87 are commonly connected to a small number of common voltage pads 80 as shown in FIG. 4. For this reason, length of the common voltage line 87 connected to the common voltage pad 80 is large thus causing a time delay problem upon application of a common voltage. In other words, a voltage difference is generated between a common voltage on the common voltage line 87 close to the common voltage pad 80 and a common voltage on the common voltage line 87 distant from the common voltage pad 80. As a result, a liquid crystal driving according to a data voltage is not smooth and thus degrades picture quality and reliability.